Design-Reuse

NPTEL CMOS Digital vlsi design good? IP Listing

The High-Speed Digital PLL is intended for applications such the Clock-Multiplying-Unit in a SERDES or a Clock-Driver where the the output frequency is not an integer multiple of the reference ...
TechRepublic

Intel’s 45nm CMOS Technology Performance Parameters in VLSI Design

The trend of CMOS technology improvement continues to be driven by the need to integrate more functions within a given silicon area. In this paper, the authors describe Intel’s 45nm technology ...
TechRepublic

Low Power VLSI CMOS Design by DCG Technique

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown ...